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TDA2SA

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SoC processor w/ highly-featured video & vision acceleration for ADAS applications

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Data sheet
Errata

TDA2SA

ACTIVE
Data sheet Order now

Product details

Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 750 Coprocessors 4 Arm Cortex-M4 CPU 32-bit Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 2-Port 1Gb switch Hardware accelerators 1 Image Video Accelerator, 4 Embedded Vision Engines (EVE) Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 750 Coprocessors 4 Arm Cortex-M4 CPU 32-bit Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 2-Port 1Gb switch Hardware accelerators 1 Image Video Accelerator, 4 Embedded Vision Engines (EVE) Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for ADAS applications
  • Video, image, and gaphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Orocessing Units (IPU)
  • Vision acceleration pac
    • Up to four Embedded Vision Engines (EVEs)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • 2-port gigabit ethernet (GMAC)
  • Enhanced Direct Memory Access (EDMA) controller
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • PCI-Express® 3.0 port with integrated PHY
    • One 2-lane gen2-compliant port
    • or two 1-lane gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC®/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRSM)
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-Pin BGA (ABC)
  • Architecture designed for ADAS applications
  • Video, image, and gaphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Orocessing Units (IPU)
  • Vision acceleration pac
    • Up to four Embedded Vision Engines (EVEs)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • 2-port gigabit ethernet (GMAC)
  • Enhanced Direct Memory Access (EDMA) controller
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • PCI-Express® 3.0 port with integrated PHY
    • One 2-lane gen2-compliant port
    • or two 1-lane gen2-compliant ports
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Five Inter-Integrated Circuit (I2C) ports
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC®/SD®/SDIO)
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRSM)
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-Pin BGA (ABC)

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm® Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm® Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.
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Technical documentation

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Type Title Date
* Data sheet TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 06 Jun 2019
* Errata TDA2x ADAS Applications Processor (Rev. J) PDF | HTML 08 Jan 2021
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05 May 2021
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24 Aug 2020
White paper Paving the way to self-driving cars with ADAS (Rev. A) 24 Jul 2020
White paper Stereo vision- facing the challenges and seeing the opportunities for ADAS (Rev. A) 24 Jul 2020
User guide TDA2x ADAS Applications Processor Public Technical Reference Manual (Rev. G) 22 Feb 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 Jan 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11 Jun 2019
Application note TDA2x/TDA2E Performance (Rev. A) PDF | HTML 10 Jun 2019
Application note The Implementation of YUV422 Output for SRV 02 Aug 2018
Application note MMC DLL Tuning (Rev. B) 31 Jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 Jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 Jun 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 May 2018
Application note TMS320C66x XMC Memory Protection 31 Jan 2018
Application note DSS Bit Exact Output (Rev. A) 12 Jan 2018
Application note Flashing Utility - mflash 09 Jan 2018
White paper Embedded low-power deep learning with TIDL 08 Dec 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 Nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 Nov 2017
Application note DSS BT656 Workaround for TDA2x (Rev. A) 03 Nov 2017
Functional safety information Safety Features on VisionSDK 26 Oct 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 Sep 2017
White paper Step into next-gen architectures for multi-camera operations in automobiles 16 Jun 2017
White paper Making Cars Safer Through Technology Innovation (Rev. A) 07 Jun 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 Dec 2016
Application note Quad Channel Camera Application for Surround View and CMS Camera Systems (Rev. A) 23 Aug 2016
Application note ADAS Power Management 07 Mar 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs 23 Feb 2016
EVM User's guide TDA2x EVM CPU Board User's Guide 09 Feb 2016
User guide Vision Application Board User's Guide 09 Feb 2016
White paper Surround view camera systems for ADAS (Rev. A) 20 Oct 2015
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 Aug 2014
White paper TI Vision SDK, Optimized Vision Libraries for ADAS Systems 14 Apr 2014
White paper TI Gives Sight to Vision-Enabled Automotive Technologies 16 Oct 2013
White paper Empowering Automotive Vision with TI’s Vision AccelerationPac 13 Oct 2013

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